Motorola MPC860 PowerQUICC, Руководство пользователя

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Part I. Overview
MOTOROLA Chapter 3. Hardware Interface Overview 3-11
BADDR[28Ð29] Output Burst AddressÑOutputs that duplicate A[28Ð29] values when one of the following
occurs:
¥ An internal master in the MPC860 initiates a transaction on the external bus.
¥ An asynchronous external master initiates a transaction.
¥ A synchronous external master initiates a single beat transaction.
The memory controller uses these signals to increment the address lines that
connect to memory devices when a synchronous external or internal master starts a
burst transfer.
AS Input Address StrobeÑInput driven by an external asynchronous master to indicate a valid
address on A[0Ð31]. The MPC860 memory controller synchronizes AS and controls
the memory device addressed under its control.
PA[15]
RXD1 Bidirectional General-Purpose I/O Port A Bit 15ÑBit 15 of the general-purpose I/O port A.
RXD1ÑReceive data input for SCC1.
PA[14]
TXD1 Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port A Bit 14ÑBit 14 of the general-purpose I/O port A.
TXD1ÑTransmit data output for SCC1. TXD1 has an open-drain capability.
PA[13]
RXD2 Bidirectional General-Purpose I/O Port A Bit 13ÑBit 13 of the general-purpose I/O port A.
RXD2ÑReceive data input for SCC2.
PA[12]
TXD2 Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port A Bit 12ÑBit 12 of the general-purpose I/O port A.
TXD2ÑTransmit data output for SCC2. TXD2 has an open-drain capability.
PA[11]
L1TXDB Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port A Bit 11ÑBit 11 of the general-purpose I/O port A.
L1TXDBÑTransmit data output for the serial interface TDM port B. L1TXDB has an
open-drain capability.
PA[10]
L1RXDB Bidirectional General-Purpose I/O Port A Bit 10ÑBit 10 of the general-purpose I/O port A.
L1RXDBÑReceive data input for the serial interface TDM port B.
PA[9]
L1TXDA Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port A Bit 11ÑBit 9 of the general-purpose I/O port A.
L1TXDAÑTransmit data output for the serial interface TDM port A. L1TXDA has an
open-drain capability.
PA[8]
L1RXDA Bidirectional General-Purpose I/O Port A Bit 8ÑBit 8 of the general-purpose I/O port A.
L1RXDAÑReceive data input for the serial interface TDM port A.
PA[7]
CLK1
TIN1
L1RCLKA
BRGO1 Bidirectional General-Purpose I/O Port A Bit 7ÑBit 7 of the general-purpose I/O port A.
CLK1ÑOne of eight clock inputs that can be used to clock SCCs and SMCs.
TIN1ÑTimer 1 external clock.
L1RCLKAÑReceive clock for the serial interface TDM port A.
BRGO1ÑOutput clock of BRG1.
PA[6]
CLK2
TOUT1
BRGCLK1 Bidirectional General-Purpose I/O Port A Bit 6ÑBit 6 of the general-purpose I/O port A.
CLK2ÑOne of eight clock inputs that can be used to clock SCCs and SMCs.
TOUT1ÑTimer 1 output.
BRGCLK1ÑOne of two external clock inputs of the BRGs.
PA[5]
CLK3
TIN2
L1TCLKA
BRGO2 Bidirectional General-Purpose I/O Port A Bit 5ÑBit 5 of the general-purpose I/O port A.
CLK3ÑOne of eight clock inputs that can be used to clock SCCs and SMCs.
TIN2ÑTimer 2 external clock input.
L1TCLKAÑTransmit clock for the serial interface TDM port A.
BRGO2ÑOutput clock of BRG2.
Table 3-1. Signal Descriptions (Continued)
Name Type Description