Motorola MPC860 PowerQUICC, Руководство пользователя

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8-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
If a bus error is encountered while loading the requested data (the critical word), then a
machine check exception is generated. If a bus error occurs while loading subsequent words
in the cache block, then the cache block is marked invalid.
After the cache block with the requested data has been loaded from memory, the
modiÞed-valid cache block in the copyback buffer is sent to the SIU to be written to
memory. If a bus error is encountered during the copyback, a machine check exception is
generated (the copyback error is an imprecise exception). The address and data in the
copyback buffer can be read as speciÞed in Section 8.3.2.1, ÒReading Data Cache Tags and
Copyback Buffer.Ó
8.6.3 Write-Through Mode
In write-through mode, store operations always update memory. The write-through mode
is used when external memory and internal cache images must always agree. Write-through
mode provides a lower worst case exception latency at the expense of average performance
(for example, if it does not have to perform ßush accesses).
8.6.3.1 Data Cache Store Hit in Write-Through Mode
In the case of a data cache store hit in write-through mode, the data is written into both the
cache block and to memory. The LRU state of the set is updated, but the state bits remain
unchanged. If a bus error is encountered during the write operation to memory, the cache
block is still updated, but a machine check exception is generated.
8.6.3.2 Data Cache Store Miss in Write-Through Mode
In the case of a store miss in write-through mode, the data is only written to memory, not
to the data cache. This is sometimes referred to as aÔno-allocateÕ store miss because the data
cache does not allocate a cache block in the cache array for the missed store operation. The
state and LRU bits remain unchanged. If a bus error is encountered during the write
operation to memory, a machine check exception is generated.
8.6.4 Write-Back Mode
In write-back mode, store operations do not necessarily update external memory. Data is
only copied to external memory when a copyback operation is required (or the cache is
deliberately ßushed). For this reason the write-back mode is the preferred mode of
operation when it is necessary to minimize external bus utilization and as a side effect,
reduce operational power consumption.
8.6.4.1 Data Cache Store Hit in Write-Back Mode
In the case of a data cache store hit in write-back mode, the cache operation depends on the
state bits of the cache block. If the store hit is to a modiÞed-valid cache block, then data is
stored in the cache block and the block stays marked modiÞed-valid. If the store hit is to a
unmodiÞed-valid cache block, then data is stored in the cache block and the block is marked
modiÞed-valid. In either case, the LRU state of the set is updated to reßect the hit.