Motorola MPC860 PowerQUICC, Руководство пользователя

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9-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
9.9 Memory Management Unit Exceptions
Table 9-22 describes MPC860-speciÞc MMU exceptions.
9.10 TLB Manipulation
The TLBs can be updated in several ways. The TLB reloading process is primarily
performed in software with some hardware assistance. The TLB replacement counter can
be conÞgured to select only from the Þrst 28 entries in each TLB. TLBs can be invalidated
by using the tlbie and tlbia instructions.
9.10.1 TLB Reload
The TLB reload (tablewalk) function is performed in the software with some hardware
assistance. It consists of the following actions:
¥ Automatic storage of the missed data or instruction EA and default attributes in
MI_EPN or MD_EPN. This value is loaded into the selected entry on a write to
MI_RPN or MD_RPN.
¥ Automatic updating of the replacement location counter to point to the entry to be
replaced. This value is placed in the index Þeld in MI_CTR and MD_CTR.
¥ As Figure 9-4 and Figure 9-5 show, the level-one pointer is generated when an
mfspr[M_TWB] is performed by concatenating the level-one table base with the
level-one index.
¥ The level-two pointer is generated when an mfspr[MD_TWC] is performed by
concatenating the level-two table base (extracted from the level-one table) with the
level-two index.
Table 9-22. MPC860-Specific MMU Exceptions
Exception Cause
ITLB miss MSR[IR] = 1 and an attempt is made to fetch an instruction from a page whose EPN cannot be translated
by the ITLB. Tablewalk software is responsible for loading information for the missed page from the
translation table. See Section 9.10.1.1, ÒTranslation Reload Examples,Ó and Section 7.1.3.2, ÒInstruction
TLB Miss Exception (0x01100).Ó
DTLB
miss MSR[DR] = 1 and an attempt is made to access a page whose EPN cannot be translated by the DTLB.
Tablewalk software is responsible for loading translation information for the missed page from the
translation table. See Section 9.10.1.1, ÒTranslation Reload Examples,Ó and Section 7.1.3.3, ÒData TLB
Miss Exception (0x01200).Ó
ITLB error The EA cannot be translated and the level-one segment or page valid bit is zero in the translation table,
the fetch access violates memory protection, or the fetch access is to guarded memory and MSR[IR] = 1.
The exact exception cause is found in SRR1. Table 7-15 describes bit assignments. If needed, it is
softwareÕs responsibility to invoke the ISI exception handler.
DTLB
error MSR[DR] = 1 and the EA of a load, store, icbi , dcbz , dcbst , dcbf , or dcbi cannot be translated and
either the level-one segment or page valid bit are zero in the translation table, the access violates
memory protection, or an attempt is made to write to a page with a negated change bit.
The DSISR explains invocation of the DTLB error exception handler. Table 7-16 describes bit
assignments. If needed, it is softwareÕs responsibility to invoke the DSI exception handler.