Motorola MPC860 PowerQUICC, Руководство пользователя

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MOTOROLA Chapter 16. Memory Controller 16-71
Part IV. Hardware Interface
4. DeÞne the UPMB (or UPMA) parameters that control the memory system in the
following sequence. For additional details, see Table 16-19.
Ñ Program the RAM array using MCR and MDR. The RAM word must be written
into the MDR before a
WRITE
command is issued to the MCR. Repeat this step
for all RAM word entries.
Ñ Initialize ORx and BRx for the required DRAM device address mapping.
Ñ ORx[MS] selects the machine to control clock cycles. Note that ORx[SAM]
controls address multiplexing for the Þrst cycle; subsequent cycles are controlled
by UPM RAM words. Also note that the AMX Þeld in the UPM RAM word
controls address multiplexing for the next clock cycle and not the current one.
Ñ Program MBMR to select the number of columns and refresh timer parameters.
Table 16-20. UPMB Register Settings
Field Register Value Comments
MS BR2 10 Selects UPMB
PS BR2 00 Selects 32-bit bus width
WP BR2 0 Allows read and write accesses
PTP MPTPR 00000010 Prescaler divided by 32
PTB MBMR 00001100 15.6
m
s at a 25-MHz clock
PTBE MBMR 1 Enables periodic timer B
AMB MBMR 001 Selects nine column address pins
DSB MBMR 01 Selects two disable timer clock cycles
GPLB4DIS MBMR 0 Disables the UPWAITB signal
RLFB MBMR 0011 Selects three loop iterations for read
WLFB MBMR 0011 Selects three loop iterations for write
SAM OR2 1 Selects column address on Þrst cycle
BIH OR2 0 Supports burst accesses