Motorola MPC860 PowerQUICC, Руководство пользователя

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MOTOROLA Chapter 16. Memory Controller 16-21
Part IV. Hardware Interface
Figure 16-18. GPCM Memory Device Interface
As Figure 16-20 shows, the timing for CS is the same as for the address lines. The strobes
for the transaction are supplied by OE or WE, depending on the transaction direction (read
or write). ORx[CSNT] controls the timing for the appropriate strobe negation in write
cycles. When this attribute is asserted, the strobe is negated one quarter of a clock before
the normal case. For example, when ACS = 00 and CSNT = 1, WE is negated one quarter
of a clock earlier, as shown in Figure 16-19. When ACS
¹
00 and CSNT = 1, WE and CS
are negated one quarter of a clock earlier, as shown in Figure 16-20.
Figure 16-19. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)
Address
CE
OE
W
Data
MEMORY
Data
WE
OE
CS
Address
MPC860
Clock
Address
TS
TA
CS
WE
OE
Data
CSNT = 1