Motorola MPC860 PowerQUICC, Руководство пользователя

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16-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
16.3.6 Parity ConÞguration
If BRx[PARE] is set, parity is generated and checked (for internal masters only) on a
per-byte basis using DP[0Ð3] for the bank. As described in Section 11.4.2, ÒSIU Module
ConÞguration Register (SIUMCR),Ó SIUMCR[OPAR] determines the type of parity. Any
parity error causes TEA to be asserted and the associated MSTAT[PER] and the
corresponding DPB or IPB bit in the transfer error status register (TESR) to be set, as
described in Section 11.4.4, ÒTransfer Error Status Register (TESR).Ó
16.3.7 Memory Bank Protection Status
The memory controller status register (MSTAT) reports write-protect violations and parity
errors for all eight banks. This protection provided through BRx[WP], is intended for
detection of erroneous accesses made by DMA from peripherals. More sophisticated
protection is provided for accesses from the core by the MMU, as described in Chapter 9,
ÒMemory Management Unit (MMU).Ó
16.3.8 UPM-SpeciÞc Registers
The machine x mode registers (MxMR) deÞne most of the global features for UPMs. The
memory command and memory data registers (MCR and MDR) are used to initialize the
UPMÕs RAM array. The memory address register (MAR) speciÞes the address to be driven
on the external bus when a UPM pattern is software-initiated by issuing a
RUN
command in
the MCR.
The memory command and memory data registers (MCR and MDR) are used to initialize
the UPMÕs RAM array. The memory address register (MAR) speciÞes the location in the
RAM array to be executed as deÞned by the MCR. Optionally, it allows a speciÞc address
pattern to be output onto A[0Ð31]. The memory periodic timer prescaler register (MPTPR)
deÞnes the divisor of the BRGCLK used as the memory periodic timer input.
The memory periodic timer prescaler register (MPTPR) deÞnes the divisor of the external
bus clock used as the memory periodic timer input.
16.3.9 GPCM-SpeciÞc Registers
There are no GPCM-speciÞc registers. All GPCM characteristics are deÞned in the
subÞelds of individual BRx and ORx registers.
16.4 Register Descriptions
The following sections describe the registers used by the memory controller.
16.4.1 Base Registers (BRx)
The base registers (BR0ÐBR7) contain the base address and address types that the memory
controller uses to compare the value on the address bus with the current address accessed.
It also includes a memory attribute and selects the machine for memory operation handling.