9-28
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part II. PowerPC Microprocessor Module
9.8.12.4 DMMU CAM Entry Read Register (MD_CAM)
When the DMMU CAM entry read register (MD_CAM), shown in Figure 9-20, is read, it
contains the effective address and page sizes of an entry indexed by
MD_CTR[DTLB_INDX]. This register is updated when a value is written to it.
Table 9-19 describes MD_CAM Þelds.
30
PV
Page validity
0 Page is not valid
1 Page is valid
31
G
Guarded memory attribute for entry
0 Nonguarded memory
1 Guarded memory
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
EPN
Reset
Ñ
R/W
R(/W)
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
EPN
SPVF
PS
SH
ASID
Reset
Ñ
R/W
R(/W)
SPR
824
Figure 9-20. DMMU CAM Entry Read Register (MD_CAM)
Table 9-19. MD_CAM Field Descriptions
Bits
Name
Description
0Ð19
EPN
Effective page number
20
SPVF Subpage validity ßags
0 Subpage 0 (address[20Ð21] = 00) is not valid
1 Subpage 0 (address[20Ð21] = 00) is valid
21
0 Subpage 1 (address[20Ð21] = 01) is not valid
1 Subpage 1 (address[20Ð21] = 01) is valid
22
0 Subpage 2 (address[20Ð21] = 10) is not valid
1 Subpage 2 (address[20Ð21] = 10) is valid
23
0 Subpage 3 (address[20Ð21] = 11) is not valid
1 Subpage 3 (address[20Ð21] = 11) is valid
Table 9-18. MI_RAM1 Field Descriptions (Continued)
Bits
Name
Description
Содержание MPC860 PowerQUICC
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