Motorola MPC860 PowerQUICC, Руководство пользователя

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MOTOROLA Chapter 37. System Development and Debugging 37-29
Part VI. Debug and Test
37.3.2.3.2 Synchronous Self-Clocked ModeÑUsing CLKOUT
The second clock mode is called synchronous self-clocked and does not require an input
clock. Instead, the port is clocked by the system clock. The DSDI input is required to meet
setup and hold time requirements with respect to CLKOUT rising edge. The data rate for
this mode is always the same as the system clock. The timing diagram in Figure 37-10
shows the serial communications synchronous self-clocked timing.
Figure 37-10. Synchronous Self-Clocked Serial Communications
37.3.2.3.3 Selection of Development Port Clock Mode
The selection of clocked or self-clocked mode is made at reset. The state of the DSDI input
is latched eight clocks after negation of SRESET. If it is latched low, asynchronous clocked
mode is enabled. If it is latched high, then synchronous self-clocked mode is enabled. The
timing diagram in Figure 37-11 shows the clock mode selection after reset.
CLKOUT
Debug port drives the ready bit onto DSDO when the core starts a read of DPIR or DPDR.
DSDI MODE CNTRL DI<0> START DI<1>
S<0> S<1> DO<0>
READY
DSDO
DO<1>
DO<N>
DO<N-1>
DO<N-2>
DO<N-3>
DI<N>
DI<N-1>
DI<N-2>
DI<N-3>
Debug port detects the start bit on DSDI and follows the ready
bit with two status bits and 7 or 32 output data bits.
Development tool drives the start bit onto DSDI (after detecting the ready bit on
DSDO when in debug mode). The start bit is immediately followed by a mode bit
and a control bit and then 7 or 32 input data bits.