MOTOROLA
Chapter 9. Memory Management Unit (MMU)
9-27
Part II. PowerPC Microprocessor Module
9.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1)
The IMMU RAM entry read register 1 (MI_RAM1), shown in Figure 9-19, contains the
protection mode information of the entry indexed by MI_CTR[ITLB_INDX]. This register
is updated only when MI_CAM is written to.
Table 9-18 describes MI_RAM1 Þelds.
28
SFP
Supervisor (supervisor) fetch permission
0 Subpage 0 (Address[20Ð21] = 00) Supervisor fetch is not permitted
1 Subpage 0 (Address[20Ð21] = 00) Supervisor fetch is permitted
29
0 Subpage 1 (Address[20Ð21] = 01) Supervisor fetch is not permitted
1 Subpage 1 (Address[20Ð21] = 01) Supervisor fetch is permitted
30
0 Subpage 2 (Address[20Ð21] = 10) Supervisor fetch is not permitted
1 Subpage 2 (Address[20Ð21] = 10) Supervisor fetch is permitted
31
0 Subpage 3 (Address[20Ð21] = 11) Supervisor fetch is not permitted
1 Subpage 3 (Address[20Ð21] = 11) Supervisor fetch is permitted
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
Reset
0
R/W
R
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Ñ
UFP
PV
G
Reset
0
Ñ
Ñ
Ñ
R/W
R
SPR
818
Figure 9-19. IMMU RAM Entry Read Register 1 (MI_RAM1)
Table 9-18. MI_RAM1 Field Descriptions
Bits
Name
Description
0Ð25
Ñ
Reserved
26
UFP
User fetch permission
0 Subpage 0 (Address[20Ð21] = 00) User fetch is not permitted
1 Subpage 0 (Address[20Ð21] = 00) User fetch is permitted
27
0 Subpage 1 (Address[20Ð21] = 01) User fetch is not permitted
1 Subpage 1 (Address[20Ð21] = 01) User fetch is permitted
28
0 Subpage 2 (Address[20Ð21] = 10) User fetch is not permitted
1 Subpage 2 (Address[20Ð21] = 10) User fetch is permitted
29
0 Subpage 3 (Address[20Ð21] = 11) User fetch is not permitted
1 Subpage 3 (Address[20Ð21] = 11) User fetch is permitted
Table 9-17. MI_RAM0 Field Descriptions (Continued)
Bits
Name
Description
Содержание MPC860 PowerQUICC
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