Motorola MPC860 PowerQUICC, Руководство пользователя

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MOTOROLA Chapter 12. Reset 12-9
Part III. Configuration
Figure 12-7 shows the conÞguration data sampling timing in relation to the HRESET and
CLKOUT signals.
Figure 12-7. Reset Configuration Sampling Timing Requirements
12.3.1.1 Hard Reset ConÞguration Word
The hard reset conÞguration word is sampled from the data bus. These bits determine the
default values of the corresponding bits in the SIUMCR, IMMR, and MSR.
Table 12-3 describes hard reset conÞguration word Þelds.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field EARB IIP Ñ BPS Ñ ISB DBGC DBPC EBDF Ñ
Default 0000_0000_0000_0000
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ
Default 0000_0000_0000_0000
NOTE: The default value is due to the internal pull-down resistor on the data bus.
Figure 12-8. Hard Reset Configuration Word
Table 12-3. Hard Reset Configuration Word Field Descriptions
Bits Name Description
0 EARB External arbitration. If this bit is set, external arbitration is assumed. If it is cleared, then internal
arbitration is performed. See Section 11.4.2, ÒSIU Module ConÞguration Register (SIUMCR).Ó
1 IIP Initial interrupt preÞx. DeÞnes the initial value of the MSR[IP] which deÞnes the interrupt table location. If
IIP is cleared (default), the MSR[IP] initial value is one; if it is set to one, the MSR[IP] initial value is zero.
See Section 5.1.2.3.1, ÒMachine State Register (MSR).Ó
2Ð3 Ñ Reserved for future use and should be allowed to ßoat.
CLKOUT
HRESET
RSTCONF
Data
1 2 3 4 5 6 7 8 0 9 10 11 12 14 15 16 17 13
Reset ConÞguration Word
Maximum Time of Reset Recognition
Maximum Setup Time of Reset Recognition
Sample Data
ConÞguration
Sample Data
ConÞguration
Sample Data
ConÞguration