
MOTOROLA
Chapter 13. External Signals
13-13
Part IV. Hardware Interface
IP_B5
LWP1
VF1
Hi-Z
J4
Bidirectional Input Port B 5ÑThe MPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 1ÑThis output reports the detection of
a data watchpoint in the program ßow executed by the core.
Visible Instruction Queue Flushes StatusÑThe MPC860
outputs VF1 with VF0 and VF2 when instruction ßow tracking is
required. VF
n
reports the number of instructions ßushed from
the instruction queue in the core.
IP_B6
DSDI
AT0
Hi-Z
K3
Bidirectional
Three-state
Input Port B 6ÑThe MPC860 senses this input and its value
and changes are reported in the PIPR and PSCR of the
PCMCIA interface. See Chapter 17, ÒPCMCIA Interface.Ó
Development Serial Data InputÑData input for the debug port
interface. See Chapter 37, ÒSystem Development and
Debugging.Ó
Address Type 0ÑThe MPC860 drives this bidirectional
three-state line when it initiates a transaction on the external
bus. If high (1), the transaction is the CPM. If low (0), the
transaction initiator is the CPU. This signal is not used for
transactions initiated by external masters.
IP_B7
PTR
AT3
Hi-Z
H1
Bidirectional
Three-state
Input Port B 7ÑThe MPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Program TraceÑTo allow program ßow tracking, the MPC860
asserts this output to indicate an instruction fetch is taking
place.
Address Type 3ÑThe MPC860 drives the bidirectional
three-state signal when it starts a transaction on the external
bus. When the core initiates a transfer, AT3 indicates whether it
is a reservation for a data transfer or a program trace
indication for an instruction fetch. This signal is not used for
transactions initiated by external masters.
OP[0Ð1]
Low
L4, L2
Output
Output Port 0Ð1ÑThe MPC860 generates these outputs as a
result of a write to the PGCRA register in the PCMCIA
interface.
OP2
MODCK1
STS
Hi-Z
L1
Bidirectional Output Port 2ÑThis output is generated by the MPC860 as a
result of a write to the PGCRB register in the PCMCIA
interface.
Mode Clock 1ÑInput sampled when PORESET is negated to
conÞgure PLL/clock mode.
Special Transfer StartÑThe MPC860 drives this output to
indicate the start of an external bus transfer or of an internal
transaction in show-cycle mode.
OP3
MODCK2
DSDO
Hi-Z
M4
Bidirectional Output Port 3ÑThis output is generated by the MPC860 as a
result of a write to the PGCRB register in the PCMCIA
interface.
Mode Clock 2ÑThis input is sampled at the PORESET
negation to conÞgure the PLL/clock mode of operation.
Development Serial Data OutputÑOutput data from the debug
port interface.
Table 13-1. Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
Содержание MPC860 PowerQUICC
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