Motorola MPC860 PowerQUICC, Руководство пользователя

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20-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
The IDMA controller continuously requests the bus until the current buffer chain is
completely transferred. The transfer terminates with an out-of-buffers error (IDSR[OB]).
To use a general-purpose timer output (TOUTx), follow these steps:
1. Externally connect a TOUTx to DREQ.
2. Clear RCCR[DRnM] (edge-sensitive).
3. Program the timer period to pace the IDMA requests (and thus bus utilization).
An interrupt handler can service the IDSR[DONE] interrupt and suspend the channel;
otherwise, the transfer terminates with an out-of-buffers error (IDSR[OB]).
20.3.7.2 IDMA Requests for Peripheral/Memory Transfers
Once an IDMA channel has been activated, an external device requests a transfer using
DREQ. The user programs the RISC controller (the CP) conÞguration register (RCCR) to
make IDMA requests either edge- or level-sensitive. The RCCR settings also determine the
priority of DREQ relative to the SCCs. See Section 19.5.1, ÒRISC Controller ConÞguration
Register (RCCR).Ó Since DREQ0 and DREQ1 are multiplexed through PC15 and PC14
respectively, the port C pin assignment register and direction register must be conÞgured as
well; see Section 34.4, ÒPort C.Ó
Level-sensitive mode maximizes IDMA channel bandwidth for devices requiring high
transfer rates. For external devices that generate a pulsed transfer signal for each data
operand, edge-sensitive requests should be used.
20.3.7.2.1 Level-Sensitive Requests
Setting RCCR[DRnM] makes the corresponding IDMA channel level-sensitive to requests.
DREQ is sampled at rising edge of the clock. The device requests service by asserting
DREQ and leaving it asserted as long as it needs service.
Each time the IDMA controller issues a bus cycle either to read or write the device, it asserts
SDACK to acknowledge the original transfer request on DREQ. The IDMA channel
continues moving data in back-to-back DMA cycles until DREQ is negated. To ensure the
correct number of DMA transfers are performed, the device must negate DREQ while the
IDMA is acknowledging the last data move, that is, while SDACK is asserted. DREQ is
sampled on the same rising edge on which TA is sampled to terminate the current cycle.
20.3.7.2.2 Edge-Sensitive Requests
Clearing RCCR[DRnM] makes the corresponding IDMA channel edge-sensitive to
requests. The edge sensitivity is further qualiÞed to detect either any edge or falling edges
only as programmed in PCINT[EDM15] and PCINT[EDM14] for DREQ0 and DREQ1,
respectively; see Section 34.4.1.5, ÒPort C Interrupt Control Register (PCINT).Ó
In edge-sensitive mode, an IDMA channel moves one data operand per request. DREQ is
sampled at each rising edge of the clock. When IDMA detects a request on DREQ, the