Motorola MPC860 PowerQUICC, Руководство пользователя

Страница: 331 / 1106

MOTOROLA Chapter 13. External Signals 13-5
Part IV. Hardware Interface
13.1 System Bus Signals
The MPC860 system bus consists of all signals that interface with the external bus. Many
of these signals perform different functions, depending on how the user assigns them. The
following input and output signals are identiÞed by their abbreviation. Each signalÕs pin
number can be found in Figure 13-2 and Figure 13-3.
Table 13-1. Signal Descriptions
Name Reset Number Type Description
A[0Ð31] Hi-Z See
Figure 13-3
Bidirectional
Three-state
Address BusÑProvides the address for the current bus cycle.
A0 is the msb. The bus is output when an internal master
starts a transaction on the external bus. The bus is input when
an external master starts a transaction on the bus.
TSIZ0
REG Hi-Z B9 Bidirectional
Three-state
Transfer Size 0ÑWhen accessing a slave in the external bus,
used (together with TSIZ1) by the bus master to indicate the
number of operand bytes waiting to be transferred in the
current bus cycle. TSIZ0 is an input when an external master
starts a bus transaction.
RegisterÑWhen an internal master initiates an access to a
slave controlled by the PCMCIA interface, REG is output to
indicate which space in the PCMCIA card is accessed.
TSIZ1 Hi-Z C9 Bidirectional
Three-state
Transfer Size 1ÑUsed (with TSIZ0) by the bus master to
indicate the number of operand bytes waiting to be transferred
in the current bus cycle. The MPC860 drives TSIZ1 when it is
bus master. TSIZ1 is input when an external master starts a
bus transaction.
RD/WR Hi-Z B2 Bidirectional
Three-state
Read/WriteÑDriven by a bus master to indicate the direction
of the data transfer. A logic one indicates a read from a slave
device and a logic zero indicates a write to a slave device.
The MPC860 drives this signal when it is bus master. Input
when an external master initiates a transaction on the bus.
BURST Hi-Z F1 Bidirectional
Three-state
Burst TransactionÑDriven by the bus master to indicate that
the current initiated transfer is a burst. The MPC860 drives this
signal when it is bus master. This signal is input when an
external master initiates a transaction on the bus.
BDIP
GPL_B5 See
Section
13.5
D2 Bidirectional
Three-state
Burst Data in ProgressÑWhen accessing a slave device in the
external bus, the master on the bus asserts this signal to
indicate that the data beat in front of the current one is the one
requested by the master. BDIP is negated before the expected
last data beat of the burst transfer.
General-Purpose Line B5ÑUsed by the memory controller
when UPMB takes control of the slave access.
TS Hi-Z F3 Bidirectional
Active
Pull-up
Transfer StartÑAsserted by a bus master to indicate the start
of a bus cycle that transfers data to or from a slave device.
Driven by the master only when it has gained the ownership of
the bus. Every master should negate this signal before the bus
relinquish. TS requires the use of an external pull-up resistor.
The MPC860 samples TS when it is not the external bus
master to allow the memory controller/PCMCIA interface to
control the accessed slave device. It indicates that an external
synchronous master initiated a transaction.