5-4
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part II. PowerPC Microprocessor Module
XER bits are described in Table 5-4.
Although divide instructions have a relatively long latency, they can update XER[OV] after
one cycle. Therefore, data dependency on the XER is limited to one cycle, although the
divide instruction latency can be a maximum of 11 clocks.
5.1.1.1.4 Time Base Registers
The time base registers (TBU and TBL) are described in Section 11.9, ÒThe PowerPC
Timebase,Ó and in Chapter 15, ÒClocks and Power Control.Ó The PowerPC architecture
does not deÞne an exception associated directly with the time base, but one is implemented
in the MPC860.
5.1.2 PowerPC RegistersÑSupervisor Registers
All supervisor-level registers implemented on the
MPC860
are SPRs, except for the machine state
register (MSR), described in Table 5-5
Table 5-4. XER Field Definitions
Bit(s)
Name
Description
0
SO
Summary overßow. Set when an instruction (except
mtspr
) sets the overßow bit (OV). Once set,
SO remains set until it is cleared by an
mtspr(XER)
or an
mcrxr
instruction. It is not altered by
compare instructions or other instructions (except
mtspr(XER)
and
mcrxr
) that cannot overßow.
1
OV
Overßow. Set to indicate that an overßow occurred during execution of an instruction. Add, subtract
from, and negate instructions with OE = 1 set OV if the carry out of the msb is not equal to the carry
out of the msb + 1 and clear it otherwise. Multiply low and divide instructions with OE = 1 set OV if
the result cannot be represented in 32 bits (
mullw
,
divw
,
divwu
) and clear it otherwise. The OV bit
is not altered by compare instructions that cannot overßow (except
mtspr(XER)
and
mcrxr
).
2
CA
Carry. Set during execution of the following instructions:
¥ Add carrying, subtract from carrying, add extended, and subtract from extended instructions set
CA if there is a carry out of the msb, and clear it otherwise.
¥ Shift right algebraic instructions set CA if any 1 bits have been shifted out of a negative operand,
and clear it otherwise.
The CA bit is not altered by compare instructions, nor by other instructions that cannot carry
(except shift right algebraic,
mtspr(XER)
, and
mcrxr
).
3Ð24
Ñ
Reserved
25Ð31
BCNT
SpeciÞes the number of bytes to be transferred by a Load String Word Indexed (
lswx
) or Store
String Word Indexed (
stswx
) instruction.
Table 5-5. Supervisor-Level PowerPC Registers
Description
Name
Comments
Serialize Access
Machine state register
MSR
See Section 5.1.2.3.1, ÒMachine State Register
(MSR).Ó
Write fetch sync
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