Technical Reference Manual
002-29852 Rev. *B
23.9.2 SCB_STATUS
Description:
Generic status
Address:
0x40600004
Offset:
0x4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits
7
6
5
4
3
2
1
0
Name
None [7:1]
EC_BUSY
[0:0]
Bits
15
14
13
12
11
10
9
8
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
Name
None [31:24]
Bit-fields
Bits Name
SW
HW
Default or
Enum
Description
0
EC_BUSY
R
W
Undefined
Indicates whether the externally clocked logic is
potentially accessing the EZ memory (this is only
possible in EZ mode). This bit can be used by SW to
determine whether it is safe to issue a SW access to
the EZ memory (without bus wait states (a blocked SW
access) or bus errors being generated). Note that the
INTR_TX.BLOCKED and INTR_RX.BLOCKED
interrupt causes are used to indicate whether a SW
access was actually blocked by externally clocked
logic.
1387
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers