Rev. 1.0, 09/01, page 569 of 904
Input capture
signal
Write signal
Address
ø
TCNT
Buffer register write cycle
T1
T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 11.51 Contention between Buffer Register Write and Input Capture
11.10.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 11.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Counter
clearing signal
TCNT input
clock
ø
TCNT
TGF
Disabled
TCFV
H'FFFF
H'0000
Figure 11.52 Contention between Overflow and Counter Clearing
Содержание H8S/2376 F-ZTAT
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