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DMA read
ø
Address bus
DMA
dead
Bus
release
DMA read
DMA read
DMA read
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)
Figure 7.27 shows a transfer example in which
7(1'
output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
ø
Address bus
DMA read
DMA read
DMA
dead
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.27 Example of Single Address Mode (Word Read) Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Содержание H8S/2376 F-ZTAT
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