Rev. 1.0, 09/01, page 234 of 904
6.11.3
Transition Timing
Figure 6.84 shows the timing for transition to the bus released state.
CPU
cycle
External bus released state
External space
access cycle
T
1
T
2
ø
Address bus
,
High-Z
High-Z
High-Z
High-Z
High-Z
[1]
[2]
[3]
[5]
[4]
[6]
[7]
[8]
[1] Low level of
signal is sampled at rise of ø.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of
signal.
[3]
signal is driven low, releasing bus to external bus master.
[4]
signal state is also sampled in external bus released state.
[5] High level of
signal is sampled.
[6]
signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
bus release while BREQOE bit is set to 1,
signal goes low.
[8] Normally
signal goes high 1.5 states after rising edge of
signal.
Data bus
Figure 6.84 Bus Released State Transition Timing
Содержание H8S/2376 F-ZTAT
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