Rev. 1.0, 09/01, page 299 of 904
DMA
read
DMA
write
ø
Address
bus
Idle
Write
Idle
Bus
release
DMA
control
Channel
Write
Idle
Transfer source
Bus
release
DMA
read
DMA
write
Bus
release
Request
[1]
[3]
[2]
[4]
[6]
[5]
[7]
Acceptance resumes
Acceptance resumes
Transfer destination
Transfer source
Transfer destination
Request
Request clear period
Request clear period
Read
Read
Minimum
of 2 cycles
Minimum
of 2 cycles
[1]
Acceptance after transfer enabling; the
pin low level is sampled on the rising edge of ø,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the
pin low level is sampled on the rising edge of ø, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.24 Example of
'5(4
'5(4
'5(4
'5(4
Pin Low Level Activated Normal Mode Transfer
'5(4
pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the
'5(4
pin low level is sampled while acceptance by means of the
'5(4
pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes,
'5(4
pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Figure 7.25 shows an example of block transfer mode transfer activated by
'5(4
pin low level.
Содержание H8S/2376 F-ZTAT
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