Rev. 1.0, 09/01, page 183 of 904
Table 6.9
Synchronous DRAM Interface Pins
Pin
With
Synchronous
DRAM Setting
Name
I/O
Function
&6
5
5$6
Row address strobe
Output
Row address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
&6
6
&$6
Column address strobe
Output
Column address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
&6
7
:(
Write enable
Output
Write enable strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
&6
8
SDRAM
φ
Clock
Output
Clock only for synchronous
DRAM
(
2(
)
(CKE)
Clock enable
Output
Clock enable signal when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
8&$6
DQMU
Upper data mask enable Output
Upper data mask enable for
16-bit continuous
synchronous DRAM space
access/data mask enable for
8-bit continuous synchronous
DRAM space access
/&$6
DQML
Lower data mask enable Output
Lower data mask enable
signal for 16-bit continuous
synchronous DRAM space
access
A15 to A0
A15 to A0
Address pins
Output
Row address/column address
multiplexed output pins
D15 to D0
D15 to D0
Data pins
I/O
Data input/output pins
DCTL
DCTL
Device control pin
Input
Output enable pin for
SDRAM
φ
Содержание H8S/2376 F-ZTAT
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