Rev. 1.0, 09/01, page 230 of 904
6.9.2
Pin States in Idle Cycle
Table 6.12 shows the pin states in an idle cycle.
Table 6.12
Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of following bus cycle
D15 to D0
High impedance
&6Q
(n = 7 to 0)
High
*
1,
*
2
8&$6
,
/&$6
High
*
2
$6
High
5'
High
(
2(
)
High
+:5
,
/:5
High
'$&.Q
(n = 1, 0)
High
('$&.Q
(n = 3 to 0)
High
Notes: 1. Remains low in DRAM space RAS down mode.
2. Remains low in a DRAM space refresh cycle.
6.10
Write Data Buffer Function
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.
Figure 6.83 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or DMA single address mode transfer continues
for two states or longer, and there is an internal access next, an external write only is executed in
the first state, but from the next state onward an internal access (on-chip memory or internal I/O
register read/write) is executed in parallel with the external address space write rather than waiting
until it ends.
Содержание H8S/2376 F-ZTAT
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