Rev. 1.0, 09/01, page xiii of xliv
8.6.2
Module Stop State ................................................................................................376
8.6.3
EDREQ
Pin Falling Edge Activation...................................................................376
8.6.4
Activation Source Acceptance .............................................................................376
8.6.5
Enabling Interrupt Requests when IRF = 1 in EDMDR.......................................377
8.6.6
ETEND
Pin and CBR Refresh Cycle ...................................................................377
Section 9 Data Transfer Controller (DTC) ....................................................... 379
9.1
Features .............................................................................................................................379
9.2
Register Configuration ......................................................................................................380
9.2.1
DTC Mode Register A (MRA).............................................................................381
9.2.2
DTC Mode Register B (MRB) .............................................................................382
9.2.3
DTC Source Address Register (SAR) ..................................................................382
9.2.4
DTC Destination Address Register (DAR) ..........................................................382
9.2.5
DTC Transfer Count Register A (CRA)...............................................................382
9.2.6
DTC Transfer Count Register B (CRB) ...............................................................383
9.2.7
DTC Enable Registers A to H (DTCERA to DTCERH)......................................383
9.2.8
DTC Vector Register (DTVECR) ........................................................................383
9.3
Activation Sources ............................................................................................................384
9.4
Location of Register Information and DTC Vector Table ................................................385
9.5
Operation...........................................................................................................................388
9.5.1
Normal Mode .......................................................................................................390
9.5.2
Repeat Mode ........................................................................................................391
9.5.3
Block Transfer Mode ...........................................................................................392
9.5.4
Chain Transfer......................................................................................................393
9.5.5
Interrupts ..............................................................................................................394
9.5.6
Operation Timing .................................................................................................395
9.5.7
Number of DTC Execution States........................................................................396
9.6
Procedures for Using DTC ................................................................................................397
9.6.1
Activation by Interrupt .........................................................................................397
9.6.2
Activation by Software ........................................................................................397
9.7
Examples of Use of the DTC ............................................................................................397
9.7.1
Normal Mode .......................................................................................................397
9.7.2
Chain Transfer......................................................................................................398
9.7.3
Chain Transfer when Counter = 0 ........................................................................399
9.7.4
Software Activation .............................................................................................400
9.8
Usage Notes ......................................................................................................................401
9.8.1
Module Stop Mode Setting ..................................................................................401
9.8.2
On-Chip RAM......................................................................................................401
9.8.3
DTCE Bit Setting .................................................................................................401
9.8.4
DMAC Transfer End Interrupt .............................................................................401
9.8.5
Chain Transfer......................................................................................................401
Section 10 I/O Ports .......................................................................................... 403
Содержание H8S/2376 F-ZTAT
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