Rev. 1.0, 09/01, page 607 of 904
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Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 13.11 Contention between TCNT Write and Increment
13.8.3
Contention between TCOR Write and Compare Match
During the T
2
state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 13.12.
Содержание H8S/2376 F-ZTAT
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