Rev. 1.0, 09/01, page 856 of 904
24.3.1
Clock Timing
Table 24.5
Clock Timing
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
ø = 8 MHz to 33 MHz, T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Max
Unit
Test Conditions
Clock cycle time
t
cyc
30.3
125
ns
Figure 24.2
Clock pulse high width
t
CH
10
—
ns
Figure 24.2
Clock pulse low width
t
CL
10
—
ns
Clock rise time
t
Cr
—
5
ns
Clock fall time
t
Cf
—
5
ns
Reset oscillation stabilization
time (crystal)
t
OSC1
10
—
ms
Figure 24.4(1)
Software standby oscillation
stabilization time (crystal)
t
OSC2
10
—
ms
Figure 24.4(2)
External clock output delay
stabilization time
t
DEXT
500
—
µ
s
Figure 24.4(1)
Clock phase difference*
t
cdif
TBD
TBD
ns
Figure 24.3
Clock pulse high width
(SDRAM
φ
)*
t
SDCH
TBD
—
ns
Figure 24.3
Clock pulse low width
(SDRAM
φ
)*
t
SDCL
TBD
—
ns
Figure 24.3
Clock rise time (SDRAM
φ
)*
t
sdcr
—
TBD
ns
Figure 24.3
Clock fall time (SDRAM
φ
)*
t
sdcf
—
TBD
ns
Figure 24.3
t
cyc
ø
t
CH
t
Cf
t
CL
t
Cr
Figure 24.2 System Clock Timing
Содержание H8S/2376 F-ZTAT
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