Rev. 1.0, 09/01, page 300 of 904
DMA
read
DMA
write
ø
Address
bus
Idle
Write
Bus release
DMA
control
Channel
Write
Transfer source
Request
[1]
[3]
[2]
[4]
[6]
[5]
[7]
Acceptance resumes
DMA
dead
Bus
release
DMA
read
DMA
write
DMA
dead
Bus
release
1 block transfer
Idle
Dead
Dead
1 block transfer
Acceptance resumes
Request
Minimum
of 2 cycles
Minimum
of 2 cycles
Transfer source
Read
Request clear period
Read
Request clear period
Transfer destination
Transfer destination
Idle
[1]
Acceptance after transfer enabling; the
pin low level is sampled on the rising edge of ø,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the
pin low level is sampled on the rising edge of ø, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of
'5(4
'5(4
'5(4
'5(4
Pin Low Level Activated Block Transfer Mode Transfer
'5(4
pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the
'5(4
pin low level is sampled while acceptance by means of the
'5(4
pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes,
'5(4
pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.10
DMA Transfer (Single Address Mode) Bus Cycles
Single Address Mode (Read): Figure 7.26 shows a transfer example in which
7(1'
output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
Содержание H8S/2376 F-ZTAT
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