Rev. 1.0, 09/01, page 227 of 904
Table 6.11
Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space
Previous Access
Next Access
ICIS2
*
2
ICIS1
ICIS0
DRMI
IDLC
Idle cycle
—
0
—
—
—
Disabled
—
1
—
—
0
1 state inserted
Normal space read
(different area)
1
2 states inserted
—
0
—
—
—
Disabled
—
1
—
—
0
1 state inserted
DRAM/continuous
synchronous DRAM
*
1
space read
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
—
0
1 state inserted
Normal space write
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
—
0
1 state inserted
Normal space read
DRAM/continuous
synchronous DRAM
*
1
space write
1
2 states inserted
—
0
—
—
—
Disabled
—
1
—
0
—
Disabled
1
0
1 state inserted
Normal space read
1
2 states inserted
—
0
—
—
—
Disabled
—
1
—
0
—
Disabled
1
0
1 state inserted
DRAM/continuous
synchronous DRAM
*
1
space read
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
0
—
Disabled
1
0
1 state inserted
Normal space write
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
0
—
Disabled
1
0
1 state inserted
DRAM/continuous
synchronous
DRAM
*
1
space read
DRAM/continuous
synchronous DRAM
*
1
space write
1
2 states inserted
0
—
—
—
—
Disabled
1
—
—
—
0
1 state inserted
Normal space read
1
2 states inserted
0
—
—
—
—
Disabled
1
—
—
—
0
1 state inserted
Normal space write
DRAM/continuous
synchronous DRAM
*
1
space read
1
2 states inserted
Содержание H8S/2376 F-ZTAT
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