Rev. 1.0, 09/01, page 159 of 904
6.6.5
Basic Timing
Figure 6.21 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
p
(precharge cycle) state, one T
r
(row address
output cycle) state, and the T
c1
and two T
c2
(column address output cycle) states.
T
p
ø
(
)
Read
Write
,
(
)
(
)
Data bus
(
)
(
)
Data bus
Address bus
T
r
T
c1
T
c2
Row address
High
High
Column address
Note: n = 2 to 5
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)
When DRAM space is accessed, the
5'
signal is output as the
2(
signal for DRAM. When
connecting DRAM provided with an EDO page mode, the
2(
signal should be connected to the
(
2(
) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the
2(
signal for DRAM
space to be output from a dedicated
2(
pin. In this case, the
2(
signal for DRAM space is output
Содержание H8S/2376 F-ZTAT
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