Rev. 1.0, 09/01, page 750 of 904
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, so acting as antennas.
17.7.4
Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of the device may be adversely affected.
•
Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss
≤
AVn
≤
Vref.
•
Relation between AVcc, AVss and Vcc, Vss
As the relationship between AVcc, AVss and Vcc, Vss, set AVcc
≥
Vcc and AVss = Vss. If
the A/D converter is not used, the AVcc and AVss pins must not be left open.
•
Vref setting range
The reference voltage at the Vref pin should be set in the range Vref
≤
AVcc.
17.7.5
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), analog
reference power supply (Vref), and analog power supply (AVcc) by the analog ground (AVss).
Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss)
on the board.
17.7.6
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN15) should be connected between AVcc and AVss as
shown in figure 17.7. Also, the bypass capacitors connected to AVcc and the filter capacitor
connected to AN0 to AN15 must be connected to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN15) are
averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit
in the A/D converter exceeds the current input via the input impedance (R
in
), an error will arise in
the analog input pin voltage. Careful consideration is therefore required when deciding the circuit
constants.
Содержание H8S/2376 F-ZTAT
Страница 24: ...Rev 1 0 09 01 page xxiv of xliv ...
Страница 38: ...Rev 1 0 09 01 page xxxviii of xliv ...
Страница 44: ...Rev 1 0 09 01 page xliv of xliv ...
Страница 60: ...Rev 1 0 09 01 page 16 of 904 ...
Страница 96: ...Rev 1 0 09 01 page 52 of 904 ...
Страница 116: ...Rev 1 0 09 01 page 72 of 904 ...
Страница 148: ...Rev 1 0 09 01 page 104 of 904 ...
Страница 284: ...Rev 1 0 09 01 page 240 of 904 ...
Страница 422: ...Rev 1 0 09 01 page 378 of 904 ...
Страница 634: ...Rev 1 0 09 01 page 590 of 904 ...
Страница 656: ...Rev 1 0 09 01 page 612 of 904 ...
Страница 668: ...Rev 1 0 09 01 page 624 of 904 ...
Страница 780: ...Rev 1 0 09 01 page 736 of 904 ...
Страница 796: ...Rev 1 0 09 01 page 752 of 904 ...
Страница 806: ...Rev 1 0 09 01 page 762 of 903 ...
Страница 808: ...Rev 1 0 09 01 page 764 of 904 ...
Страница 921: ...Rev 1 0 09 01 page 877 of 904 ø tBRQOD tBRQOD Figure 24 24 External Bus Request Output Timing ...
Страница 938: ...Rev 1 0 09 01 page 894 of 904 ...