Rev. 1.0, 09/01, page 162 of 904
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
rw
states, in which row address output is maintained,
to be inserted between the T
r
cycle, in which the
5$6
signal goes low, and the T
c1
cycle, in which
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the
5$6
signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.24 shows an example of the timing when one T
rw
state is set.
T
p
ø
(
)
Read
Write
,
(
)
(
)
Data bus
(
)
(
)
Data bus
Address bus
T
r
T
rw
T
c1
T
c2
Row address
Column address
High
High
Note: n = 2 to 5
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0)
Содержание H8S/2376 F-ZTAT
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