4-36
120 Series Maternal/Fetal Monitor
Revision B
2015590-001
Theory of Operation: NBP Board
connected to the A/D converter through three FET switches used to select an input
for conversion.
MUX and A/D
The MUX is composed of a DG444 quad FET switch pack (U15). Three switches in
this device are used. The drain leads connect to the individual input signals, and the
sources connect together and go to a unity gain noninverting amplifier (U12).
Control for each switch comes from individual port output lines from the processor.
The amplifier output provides the A/D input. The A/D is a Burr Brown ADS7806
12-bit converter (U11) with an 8-bit processor output and a configurable input
voltage range. The input voltage range for this application is selected to be ±10 V.
The processor reads the high byte on even addresses, and the low byte on odd.
Conversion is started by a write to the A/D read address. The BUSY line from the
A/D which indicates a conversion in process, connects to an input port of the
processor. The A/D also contains a precision 2.5 V reference which is used to
generate the 10 V bridge drive and pressure offset voltage. The 10 V is generated
from the 2.5 V using a non-inverting amplifier (U12) with a gain of 4 and an output
transistor current driver (Q4).
Microcontroller and Host Interface
The microcontroller used in this circuit is a Motorola MC68332 (U10), configured
for 8-bit bus operation. A total of 128 kB each of flash ROM and SRAM is installed
on this board. The processor clock is provided using a 31.2 kHz crystal (X2) and the
internal PLL circuitry of the controller. Power-on reset is provided by a Maxim
MAX707 chip (U4). With the exception of the six I/O port lines used for MUX
selection and the AC signal clamps, other control functions of devices like the
valves and pump are done through the NBP ASIC (U9). The processor accesses this
device through the 8-bit data bus. Host communications are provided by the SCI
interface of the U10. It excepts/provides RS-232C formatted 5 V serial data.
Communications formats are designed to provide functional equivalence to
DINAMAP products.
Pump/Valve Control
Primary control of the pump and valves is done through the NBP ASIC (U9). This
ASIC provides a timeout control for the pump and valves, overpressure pump/valve
disable utilizing an external overpressure switch, and provides the processor access
to sequence the valves on and off and control the pump’s speed and activation.
Three regulators (one for the pump and one for each of the two valves) that provide
the supplies to the pump and valves are enabled by a control line from a processor
port. Once the supplies are activated, sequencing of these devices is provided by
output ports on the ASIC which control transistors switches. These transistors
provide a ground return path for the activated device. In the case of a timeout or an
overpressure fault, the ASIC will automatically shut off the pump and open the
valves without processor intervention. Pump speed is controlled with the ASIC
using output ports to control two transistor switches which change the feedback
voltage to the pump regulator. The change in feedback voltage causes an increase or
decrease in the regulator’s output voltage which in turn controls the pump’s output
air volume.
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