GE Corometrics 126, Руководство по обслуживанию

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4-26 120 Series Maternal/Fetal Monitor Revision B
2015590-001
Theory of Operation: DSP Board
The shared memory consists of a 8k x16 dual port RAM (U29) which has contention
logic. The processor is given priority to read or write data into the RAM without
waiting. In a contention situation, the graphics side of the memory could possibly
receive wrong or changing data; however since data is changing anyway, this is not
noticed. Also, contention occurs only when both address are the same, about once
or twice a second in this case. Since the dual port RAM cannot give priority to
either side if one side accesses before the other, the PAL accomplishes this by gating
the processor side BUSY signal (normally holds off the processor) with the graphics
side chip select such that the graphics chip select is turned off immediately.
The graphics section consists of the graphics generator PAL (U13), oscillator
(OSC1), and output synchronization latch (U1). The graphics generator contains a
divide-by-four pre-scaler, a horizontal counter chain, a vertical counter chain,
decoding logic to control each counter operation, a 16-bit shift register, and control
logic for pattern, inverse, and scan stop functions. The El panel size is 320 bits
across by 256 lines down. The horizontal counter was set up to count to 335 (16 bits
or one word of off time for horizontal) then reset to zero. The horizontal waveform
is generated off the counter by decoding 320. The horizontal high time is then 20
words and off time one word. The output of the horizontal counter clocks the
vertical counter chain. A decode of 262 is created to form the vertical pulse as well
as clear the vertical counter. A count of 262 was used instead of 256 to meet the EL
panel specification for frame rate (72 Hz maximum). After line 256, the EL panel
does not display information until a vertical occurs. The load pulse for the shift
register is created by decoding the least significant 4 bits of the horizontal counter
and the video clock. The shared RAM graphics side chip select is created in the
same fashion. Data for the shift register (from shared RAM) first is gated through
the pattern logic before entering the shift register. The pattern logic simply forces
each alternating bit to a 1/0 pattern. This creates an on/off pattern of lines down the
screen. To further enhance the pattern, the output of the shift register data is
inverted every other horizontal line. This creates an alternating pixel pattern in both
horizontal and vertical directions. The output of the shift register also contains logic
to invert data. The stop scan function allows the processor to update the screen (i.e.
moving bar) without having the graphics scan the changing data. This function is
accomplished by stopping the timing generator including the video clock. Stopping
the scan for less than 10% of the frame rate (14 ms frame rate) can be accomplished
without causing the video to degrade.