GE Corometrics 126, Руководство по обслуживанию

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4-24 120 Series Maternal/Fetal Monitor Revision B
2015590-001
Theory of Operation: DSP Board
DSP Board
NOTE:
Refer to “Chapter 14, Replacement Parts” , to determine the correct DSP
Board for your monitor.
Functional Overview
This board consists of two independently functioning modules: DSP and front panel
interface.
The DSP section processes analog and digital data from the front ends and interfaces
to the main processor. The ECG and ultrasound analog information is processed and
heart rates are outputted to the Main Motherboard via a shared memory. Digital
pressure information is received, processed, and also sent to the shared memory.
The front panel interface section provides the interface between the front panel
switch board and the main processor as well as the EL display panel and the
processor. The switch interface section consists mainly of buffers. The display
section consists mainly of a shared memory and timing generator PAL.
DSP Section
Control Module
This section consists of the TMS30C52 DSP processor (U27), 32k x 16 system
RAM (U10, U11), 128K x 16 flash ROM (U8, U9), and two address decoder PALs
(U18 and U19). Decoder PAL U19 selects the RAM, flash ROM, and the front end
control status locations BCS0*–BCS3*. RAM is decoded using DS* (data strobe);
flash ROM is decoded using PS* (program strobe); and the remaining lines are
decoded using IS* (I/O strobe). Pal U18 selects the I/O for the status/control
section, A/D read and start convert signals, and pressure channel select and start
convert signals. The program address space is 64k minus the bottom 8k which is
used for program RAM. The flash ROM runs with one wait state. The second half
of the flash ROM can be addressed by toggling D10 of the control port (tied to A16
of the flash ROM). All 32k x16 system RAM is accessed as zero wait state data
memory. In addition, the lower 8k of the system memory is double mapped to the
last 8k of the 64k program memory.
Watchdog Module
The watchdog module consists of processor supervisor chip max694 (U26). This
chip provides a power-on reset function and a watchdog timer function.
The RESET line is pulled low for 50 ms for both a power-on and watchdog reset.
The watchdog timer times out after a 1-second minimum.