GE Corometrics 126, Руководство по обслуживанию

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Revision B 120 Series Maternal/Fetal Monitor 4-77
2015590-001
Theory of Operation: Isolated Power Supply Board
External Synchronization
The external synchronization of the LT1270 (U4) occurs when its Vc pin is pulled to
ground with an external transistor. To avoid disturbing the DC characteristics of the
internal error amplifier, the width of the synchronizing pulse must be under 1 µs.
The circuitry for synchronizing is comprised of Q1, D1-3, C2, C3, R1, R24-26, and
U5.
The external synchronizing clock (72 kHz) is connected to an input of a two input
AND gate (U5). The other input is connected to a reset signal (RESET*). The
reason for the reset signal is because upon start up the controller (U4) must be
allowed to first free-run before it can be externally synchronizing. Holding the reset
line low will inhibit synchronizing. Resistors R28 and R29 are to prevent U5 pins
12 and 13 from floating during board testing. The remaining three AND gates from
U5 are paralleled, each with a 47 W output resistor, to provide as much drive current
as possible into the synchronizing circuitry. U5 is powered from VR1, a 5
Vdc regulator.
C3 and R1 differentiate the 72 kHz clock. On positive going edges of the clock a
narrow positive pulse is applied to the base of transistor Q1. The values of C3 and
R1 determine the width of this pulse. D1 and D2 block the negative portion of the
differentiated signal. D3 speeds up the turn off time of Q1.
Fly-back Transformer, Output Rectification, and Filtering
The fly-back transformer (T1) was constructed to meet the creepage requirements of
I.E.C. 601-1. Its breakdown voltage is 3000 VAC (1 minute, primary to secondary).
The primary inductance is 30 µH (at 1 kHz). At the supplies maximum load, the
peak primary current is approximately 5.9 A.
The output rectifiers are D7–9. They are silicon ultra-fast switching rectifiers with a
maximum peak reverse voltage of 100 V. The main ±15 V outputs (+15VISO, –
15VISO) and the secondary ±15 V outputs (+15VISO2, –15VISO2) each use one
220 µF aluminum electrolytic capacitors for their main filtering (C22, 23,11,12).
One 220 µF capacitor connected has an equivalent ESR of 0.12 W at 72 kHz. Each
output utilizes a linear regulators (VR2, 3,5,6,7) to obtain their outputs.
C15,16,30,32,34 provide the necessary output filtering for the linear regulators. The
regulators (LM2940CT-15, LM2990T-15) have internal short circuit and thermal
protection. Short circuit protection for the total supply is provided by the in-rush
current limiter. See
“Short Circuit Protection” on page 4-79 .
Because the linear regulators for the +15VISO, –15VISO outputs are not located
close to the filter capacitors, C29 and C30 were used to prevent any instability in
these regulators.
The +15VISO2 and –15VISO2 outputs have load resistors on the supply (R18,19).
These resistors keep the unregulated outputs of this lightly loaded supply from
getting too high. The filter capacitors are rated for 25 Vdc. Without the load
resistors, the unregulated voltage could exceed this rating.
For further EMI reduction, RC series networks (R16, C27, R17, C26) are placed
across each secondary output. Resistors R18–21 are used to guarantee a minimum
load for each output. Both isolated grounds (ISOGND and ISOGND2) are meant to
be isolated from each other. To keep them isolated, yet at approximately the same