GE Corometrics 126, Руководство по обслуживанию

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Revision B 120 Series Maternal/Fetal Monitor 4-53
2015590-001
Theory of Operation: UA/FECG Board
The output from the FECG amplifier is coupled from the isolated circuitry to
unisolated circuitry by isolation amplifier U2. This device is a capacitive coupled
VCO/PLL type design that provides unity gain output with a frequency response of
DC to about 500 Hz and has a breakdown voltage of 8000 V-pk. The output from
U2 is low-pass filtered at 90 Hz by a two-pole filter consisting of U1, C52, C54,
R75, and R76. The filtered output is further amplified by another stage of U1 that
provides a non-inverting gain of 10 for the 80 dB FECG output that connects to the
rear panel jack of the monitor.
The filtered output also drives two other circuit blocks that provide the different
filtering and gain adjustments necessary to do either FECG or MECG processing
from the same front end amplifier. The last two stages of U1 perform the filtering
and gain correction for the FECG processing. The first stage consists of U1, C58,
C59, C60, R82, R83, and R84 which form a 3-pole 20 Hz high-pass filter. The last
stage of U1 amplifies the output from the high-pass filter by providing a gain of 15.
This output connects to the DSP Board for signal processing and rate detection.
Isolated UA Circuitry
The isolated UA section of this board consists of an instrumentation amplifier U12,
amplifier and low-pass filter from two sections of U22, a 12-bit serial A/D converter
U9, and a precision 4 V bridge power supply from another section of U22. The
differential output from the IUP or TOCO bridge is amplified by the instrumentation
amplifier U12 which has a gain of 100. The output of U12 is additionally amplified
by a stage of U22 with a gain of 15, making the total gain of the UA front end 1500.
After amplification, the UA signal is filtered by a unity gain two-pole 10 Hz low-
pass filter consisting of U22, R16, R17, C9, C10, and C11. The output from the
low-pass filter connects to the input of a 12-bit serial A/D converter, U9. The
converter is configured for an input range of ±10 V. At the falling edge of the A/D
convert pulse, the input level to the A/D is held and a conversion is started. Some
time after the start of conversion (approximately 450 ns), the A/D will begin
generating the 12 clock pulses and synchronized data to serially shift out the results
from the previous conversion. The supply for the IUP or TOCO bridge is derived
from the 2.5 V reference in the A/D converter. This is amplified by a stage of U22
to 4.00 V with transistor Q1 providing current gain to enable the supply to provide
the drive necessary for the bridge. With a 4 V drive, the scaling of the bridge is 20
µV/mmHg.
Resistor R3, R4, R5, R6, and capacitors C1, C2, and C3 comprise a differential low-
pass input filter for the bridge amplifier U12. This keeps high frequency energy
from effecting the operation of this stage. D1, D2, D3, and D4 limit the differential
input voltage to U1 from exceeding ±1.2V.