GE Corometrics 126, Руководство по обслуживанию

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4-20 120 Series Maternal/Fetal Monitor Revision B
2015590-001
Theory of Operation: Main Motherboard
Control Block
The control block contains the basic processing engine (68302), system RAM,
system ROM, address decoder, power-on reset module, oscillator, and control/setup
section. The 68302 device (U33) contains a 68000 core processor, chip select logic
(CS0/–CS3/), two timers, DTACK generation/wait state logic, a general purpose
DMA controller, watchdog timer, interrupt controller, three USARTs with six
dedicated DMA channels for transmit/receive, three-wire serial link, and 1152 bytes
of dual port RAM. The clock for the 68302 is derived from a 20 MHz crystal (X3)
connected to the processor. The processor system clock is output from the processor
via the CLKO pin. This clock is then buffered and sent to the Options Interface,
DSP Interface, and local 16V8H control PAL (U34). The power-on reset function is
accomplished through MAX691A supervisory chip (U24). This chip performs four
functions. First, at power-up, a 200 ms reset pulse is generated. The second function
is a watchdog timer which must be written every 100 ms or faster, and up to 1.6
seconds after reset. The third function provides power supply monitoring, which
resets the system if the supply falls below 4.65 V. The fourth function provides an
early power fail detection status line (routed to PB11, pin 121) of U33). The
comparator senses a power fail when the reg20 V falls below 18 V. This
gives the processor 40 ms to shut down the monitor. The processor can also be reset
by the Host Board through the HRES* line and AND gate U37. The serial output
channel is used to write to the recorder printhead shift register. Each time a byte is
sent from this port, eight clocks are generated on the RECLK line (pin 77 of U33),
2.5 MHz serial rate, along with the serial data RECDATA (pin 78 of U33). One of
the two internal timers is used externally for the ECG audio (pin 113 of U33). For
communications, one USART is used for the Corolan interface, and the other two
are used for external RS-232C communication. The address decoder consists of a
7032 PLD (U20), which basically divides up the four programmable chip selects
(CS0/–CS3/) from the processor into all of the board selects. The processor (U33) is
programmed such that CS0/ is a 4 MB space with internally generated DTACK and
zero wait states. This space is then divided further by the 7032 (U20) to form the
system flash ROM, RAM, and SP2* (spare chip select which goes to the options
interface) chip selects. CS1* is a 2 MB space with external DTACK expected. The
7032 forms the 68C94 QUART chip select and SP1* (spare select to options
interface). CS2* is a 2 MB select with a six wait state internal DTACK. The 7032
generates the decodes for audio DACs, battery RAM, DSP shared memory, and
SP4* (spare select to options interface) from CS2*. CS3* is a 2 MB select with a
two wait state internal DTACK. The 7032 generates the control/dip switch, front
panel, recorder, and SP3* (spare select to options interface) chip selects from CS3*.
The 16V8 PAL (U34) converts the processor control lines to form upper and lower
read/write lines. Corolan transmit control is also accomplished with this 16V8. The
control/setup section consists of two 8-bit latches (U21, U22) for I/O control and a
buffer (U3) for reading dip switches (SW1). The control latch allows control of the
watchdog timer, battery RAM enable, audio enables, reset lines for peripherals, and
Corolan control lines. The system memory consists of two 512k x 8 flash ROMS
(U31, U32), two 128k x 8 static RAMs (U18, U19) upgradable to 512k x 8 RAMs,
and one 8k x 8 battery RAM (U30).
Corolan Module
The Corolan section consists of the network transceiver section and the address
detection circuitry. Network data flows through the common mode transformer (T2)
to the isolation pulse transformer PE5156 (T1) to the transceiver/manchester
encoder-decoder (U16). Serial data and clocks are then fed to the USART in U33.