GE Corometrics 126, Руководство по обслуживанию

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Revision B 120 Series Maternal/Fetal Monitor 4-25
2015590-001
Theory of Operation: DSP Board
Status/Control Module
This module consists of control latches (U5, U7) and a status buffer (U6). The
control latch has bits which select the input multiplexor (MUX0–MUX3), control
the high/low bytes coming from the A/D (BYTE), reset the front end (RESFR*),
enable the front-end control interface (U1 CNTRLEN*), control flash ROM paging,
and control the pressure channel interface (IUPCLR*). The status buffer reads in
the interrupt line (INTL*) from the shared memory (on Main Motherboard), BUSY*
line from the A/D and the pacemaker pulse (PACER*).
Front-End Control/Status Interface
This section consists of a transceiver (U20) and a buffer (U14). The transceiver
allows 8 bit bi-directional data to be transferred to and from the front-end modules.
Data is controlled by the buffered read (BRD*), write (BWR*), chip select lines
(CS0*–CS3*), and address lines (BA0–BA1). Status information such as modes
and control information for ultrasound, FECG, MECG, and UA are read through this
port.
IUP Interface
The IUP interface section consists of two 8-bit serial-in parallel-out shift registers
(U16, U17) and a start conversion line (CVRT*). The process is started by the
320C52 processor (U27) pulsing the CVRT* line which connects to a serial A/D in
the pressure channel front end. Twelve data clocks are then issued from the A/D,
clocking in the 12-bit result. The shift register clock for U16 and U17 is delayed
through R12/C10 and U15 to provide the latch clock for U16 and U17. Data is then
read by the processor through the IUP chip select line. As a second function, the
clock signal is also used to clock serial mode and status information across the
isolation barrier from the UA/FECG and MECG Boards. Information to and from
the ECG Boards is transferred via the status/control module.
Analog Conversion Module
The analog conversion module consists of an input multiplexor (U21), a multiplexor
buffer amplifier (U22), a 12-bit A/D chip (U23), and a data buffer (U24). The
multiplexor takes in the two ultrasound envelope signals, FECG and MECG signals,
fetal movement detection signals, fetal movement envelope signals, telemetry
signals, ECG signals, TOCO signals, analog ground, and +10 V and –5 V reference
signals for test and calibration. The +10 V reference is also used by the ultrasound
module. Data out of the multiplexor is then buffered by one section of U22 and
passed to the A/D chip U23. The 2.5 V reference in the A/D is buffered and
amplified to +10 V and –5 V using two more sections of U22. A/D output data is
read by the processor through a buffer (U24) one byte at a time. Byte selection is
controlled by the BYTE line going to U23, pin 24.
Front Panel Interface Section Theory
EL Panel Interface
The interface consists of two major sections: shared memory and graphics
generator.