
18
Hardware Reference NS9215
Buffer length ...........................................................................340
Destination address [pointer]........................................................340
Status ....................................................................................341
Wrap (W) bit............................................................................341
Interrupt (I) bit.........................................................................341
Last (L) bit ..............................................................................341
Full (F) bit ..............................................................................341
Descriptor list processing....................................................................341
Peripheral DMA read access.................................................................342
Determining the width of PDEN .....................................................342
Equation variables .....................................................................342
Peripheral DMA single read access ..................................................343
Peripheral DMA burst read access...................................................343
Peripheral DMA write access................................................................343
Determining the width of PDEN .....................................................344
Peripheral DMA single write access .................................................344
Peripheral DMA burst write access..................................................344
Peripheral REQ and DONE signaling........................................................344
REQ signal...............................................................................344
DONE signal .............................................................................345
Special circumstances.................................................................345
Static RAM chip select configuration ......................................................345
Static ram chip select configuration................................................345
Control and Status registers ................................................................346
Register address map .................................................................346
DMA Buffer Descriptor Pointer..............................................................346
DMA Control register .........................................................................347
DMA Status and Interrupt Enable register ................................................350
DMA Peripheral Chip Select register.......................................................352
C h a p t e r 8 : A E S D a t a E n c r y p t i o n / D e c r y p t i o n M o d u l e . . . . . . . . . . . 3 5 5
Features.................................................................................355
Block diagram ..........................................................................356
Data blocks .............................................................................356
AES DMA buffer descriptor ..................................................................356
AES buffer descriptor diagram.......................................................357
Source address [pointer] .............................................................357
Source buffer length ..................................................................357
Destination buffer length.............................................................357
Destination address [pointer]........................................................357
AES control .............................................................................357
AES op code.............................................................................358
WRAP (W) bit ...........................................................................358
Interrupt (I) bit.........................................................................358
Содержание NS9215
Страница 1: ...NS9215 Hardware Reference 90000847_C Release date 10 April 2008...
Страница 3: ......
Страница 4: ......
Страница 26: ...26 Hardware Reference NS9215...
Страница 44: ...P I N O U T 26 5 System clock 44 Hardware Reference NS9215 System clock drawing...
Страница 52: ...P I N O U T 26 5 Power and ground 52 Hardware Reference NS9215...
Страница 80: ...I O C O N T ROL M O D U L E Memory Bus Configuration register 80 Hardware Reference NS9215...
Страница 136: ...WOR KI N G W I TH T H E C P U Noncachable instruction fetches 136 Hardware Reference NS9215...
Страница 202: ...S Y S T E M C O N T RO L M OD U L E RTC Module Control register 202 Hardware Reference NS9215...
Страница 260: ...M E MO R Y C O N T ROL L E R StaticMemory Turn Round Delay 0 3 registers 260 Hardware Reference NS9215...
Страница 354: ...E X T E R N A L D M A DMA Peripheral Chip Select register 354 Hardware Reference NS9215...
Страница 362: ...A E S D AT A E N C R Y P T I O N D E C R Y P T I O N M O D U L E CCM mode 362 Hardware Reference NS9215...
Страница 384: ...I O HU B M OD UL E Module Direct Mode TX Data Last FIFO 384 Hardware Reference NS9215 31 March 2008...
Страница 414: ...S E R I A L C ON T RO L M O D U L E U ART UART Modem Status register 414 Hardware Reference NS9215...
Страница 446: ...S E R I A L C ON T RO L M O D U L E S PI SPI timing characteristics 446 Hardware Reference NS9215...
Страница 472: ...R E A L TI M E C L O C K M O D U L E General Status register 472 Hardware Reference NS9215...
Страница 512: ...TI M I NG Clock timing 512 Hardware Reference NS9215...
Страница 514: ...PA CKA GING Processor Dimensions 514 Hardware Reference NS9215 P r o c e s s o r D i m e n s i o n s...
Страница 515: ...PA CKA GING Processor Dimensions www digiembedded com 515...
Страница 516: ...PA CKA GING Processor Dimensions 516 Hardware Reference NS9215...