1083
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
41.7.4
DACC Channel Disable Register
Name:
DACC_CHDR
Address:
0x4003C014
Access:
Write-only
This register can only be written if the WPEN bit is cleared in
DACC Write Protect Mode Register
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then re-enabled during a conver-
sion, its associated analog value and
its
corresponding EOC flags in DACC_ISR are unpredictable.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
CH1
CH0
Содержание SAM4S Series
Страница 44: ...44 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...
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Страница 1105: ...1105 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...
Страница 1142: ...1142 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 3 100 ball VFBGA Package Drawing ...
Страница 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...
Страница 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...