Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR.
As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only
when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a
reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
13.4.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this
occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the
field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts
2
(ERSTL+1)
Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs
and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that
the NRST line is driven low for a time compliant with potential external devices connected on the
system reset.
As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the
system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
13.4.3 Brownout Manager
The Brownout manager is embedded within the Supply Controller, please refer to the product
Supply Controller section for a detailed description.
13.4.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
13.4.4.1 General Reset
A general reset occurs when a Power-on-reset is detected, a Brownout or a Voltage regulation
loss is detected by the Supply controller. The vddcore_nreset signal is asserted by the Supply
Controller when a general reset occurs.
All the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset.
As the RSTC_MR is reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL
defaults at value 0x0.
Figure 13-3 shows how the General Reset affects the reset signals.