Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
25.10.3.2 Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or
exited, after the end of the current transfer (see
“Slow Clock Mode” on page 444 ).
25.10.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and
write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states
when they are to be inserted. See
Figure 25-13 on page 430 .
25.11 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access:
• Before starting a read access to a different external memory
• Before starting a write access to the same device or to a different external one.
The Data Float Output Time (t
DF
) for each external memory device is programmed in the
TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of
TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the
external device releases the bus, and represents the time allowed for the data output to go to
high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long t
DF
will not slow down the execution of a program from internal
memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE
fields of the SMC_MODE register for the corresponding chip select.
25.11.1 READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turn-
ing off the tri-state buffers of the external memory device. The Data Float Period then begins
after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles.
When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives
the number of MCK cycles during which the data bus remains busy after the rising edge of NCS.
Figure 25-17 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1),
assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 25-18 shows the read oper-
ation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3.