Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
27.1.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLLs (PLLA, PLLB) allow multiplication of the divider’s outputs. The PLL clock signal has a
frequency that depends on the respective source signal frequency and on the parameters DIV
(DIVA, DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is
(MUL + 1)/DIV. When MUL is written to 0, the PLL is disabled and its power consumption is
saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA,
LOCKB) bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field
(PLLACOUNT, PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR, CKGR_PLLBR) are loaded in
the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it
reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the pro-
cessor. The user has to load the number of Slow Clock cycles required to cover the PLL
transient time into the PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC
Master Clock Register (PMC_MCKR).
It is forbidden to change 4/8/12 MHz Fast RC oscillator, or main selection in CKGR_MOR regis-
ter while Master clock source is PLL and PLL reference clock is the Fast RC oscillator.
The user must:
• Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR.
• Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
• Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in
PMC_IER.
• Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
• Wait for PLLRDY.
• Switch back to PLL.