Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
11.4.1.4 General-purpose Registers
R0-R12 are 32-bit general-purpose registers for data operations.
11.4.1.5 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indi-
cates the stack pointer to use:
• 0 = Main Stack Pointer (MSP). This is the reset value.
• 1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address 0x00000000.
11.4.1.6 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function
calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF
.
11.4.1.7 Program Counter
The Program Counter (PC) is register R15. It contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x00000004.
Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.
Link Register LR Read-write Either 0xFFFFFFFF
Program Counter PC Read-write Either See description
Program Status Register PSR Read-write Privileged 0x01000000
Application Program Status Register APSR Read-write Either 0x00000000
Interrupt Program Status Register IPSR Read-only Privileged 0x00000000
Execution Program Status Register EPSR Read-only Privileged 0x01000000
Priority Mask Register PRIMASK Read-write Privileged 0x00000000
Fault Mask Register FAULTMASK Read-write Privileged 0x00000000
Base Priority Mask Register BASEPRI Read-write Privileged 0x00000000
CONTROL register CONTROL Read-write Privileged 0x00000000
Table 11-2. Core Processor Registers
Register Name Access
(1)
Required
Privilege
(2)
Reset