Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
37.6.2.7 Synchronous Channels
Some channels can be linked together as synchronous channels. They have the same source
clock, the same period, the same alignment and are started together. In this way, their counters
are synchronized together.
The synchronous channels are defined by the SYNCx bits in the “PWM Sync Channels Mode
Register” (PWM_SCM). Only one group of synchronous channels is allowed.
When a channel is defined as a synchronous channel, the channel 0 is automatically defined as
a synchronous channel too, because the channel 0 counter configuration is used by all the syn-
chronous channels.
If a channel x is defined as a synchronous channel, it uses the following configuration fields of
the channel 0 instead of its own:
• CPRE0 field in PWM_CMR0 register instead of CPREx field in PWM_CMRx register (same
source clock)
• CPRD0 field in PWM_CMR0 register instead of CPRDx field in PWM_CMRx register (same
period)
• CALG0 field in PWM_CMR0 register instead of CALGx field in PWM_CMRx register (same
alignment)
Thus writing these fields of a synchronous channel has no effect on the output waveform of this
channel (except channel 0 of course).
Because counters of synchronous channels must start at the same time, they are all enabled
together by enabling the channel 0 (by the CHID0 bit in PWM_ENA register). In the same way,
they are all disabled together by disabling channel 0 (by the CHID0 bit in PWM_DIS register).
However, a synchronous channel x different from channel 0 can be enabled or disabled inde-
pendently from others (by the CHIDx bit in PWM_ENA and PWM_DIS registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the
bit SYNCx to 1 while it was at 0) is allowed only if the channel is disabled at this time (CHIDx = 0
in
PWM_SR register)
. In the same way, defining a channel as an asynchronous channel while it is
a synchronous channel (by writing the SYNCx bit to 0 while it was 1) is allowed only if the chan-
nel is disabled at this time.
The field UPDM (Update Mode) in the PWM_SCM register allow to select one of the three meth-
ods to update the registers of the synchronous channels:
• Method 1 (UPDM = 0): the period value, the duty-cycle values and the dead-time values must
be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPDx).The update is triggered at the next PWM period as
soon as the bit UPDULOCK in the
“PWM Sync Channels Update Control Register”
(PWM_SCUC) is set to 1 (see “Method 1: Manual write of duty-cycle values and manual
trigger of the update” on page 920 ).
• Method 2 (UPDM = 1): the period value, the duty-cycle values, the dead-time values and the
update period value must be written by the CPU in their respective update registers
(respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPD). The update of the
period value and of the dead-time values is triggered at the next PWM period as soon as the
bit UPDULOCK in the
“PWM Sync Channels Update Control Register” (PWM_SCUC) is set
to 1. The update of the duty-cycle values and the update period value is triggered
automatically after an update period defined by the field UPR in the
“PWM Sync Channels