Atmel SAM4S Series, Предварительный информационный лист

Страница: 932 / 1163

932
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 37-19. Synchronized Update of Comparison Values and Configurations
37.6.5.6 Interrupts
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can
be generated at the end of the corresponding channel period (CHIDx in the PWM_ISR1 regis-
ter), after a fault event (FCHIDx in the PWM_ISR1 register), after a comparison match (CMPMx
in the PWM_ISR2 register), after a comparison update (CMPUx in the PWM_ISR2 register) or
according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a
read operation in the PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt
remains active until a read operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and
PWM_IER2 registers. A channel interrupt is disabled by setting the corresponding bit in the
PWM_IDR1 and PWM_IDR2 registers.
37.6.5.7 Write Protect Registers
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the field WPCMD in the
“PWM Write Protect Control Register”
on page 963 (PWM_WPCR). They are divided into 6 groups:
• Register group 0:
– “PWM Clock Register” on page 937
• Register group 1:
– “PWM Disable Register” on page 938
PWM_CMPVUPDx Value
Comparison Value
for comparison x
User's Writing
PWM_CMPVx
End of channel0 PWM period and
end of Comparison Update Period
PWM_CMPMUPDx Value
Comparison configuration
for comparison x
PWM_CMPMx
User's Writing
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPMx written