Atmel SAM4S Series, Предварительный информационный лист

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1138
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 42-29. Two-wire Serial Bus Timing
42.11.9 Embedded Flash Characteristics
The maximum operating frequency is given in tables 42-50 to 42-53 below but is limited by the Embedded Flash access
time when the processor is fetching code out of it. The tables 42-50 to 42-53 below give the device maximum operating fre-
quency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to
access the Embedded Flash Memory.
The embedded flash is fully tested during production test, the flash contents are not set to a known state prior to shipment.
Therefore, the flash contents should be erased prior to programming an application.
Table 42-50. Embedded Flash Wait State VDDCORE set at 1.08V and VDDIO 1.62V to 3.6V @85C
FWS Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 16
1 2 cycles 33
2 3 cycles 50
3 4 cycles 67
4 5 cycles 84
5 6 cycles 100
Table 42-51. Embedded Flash Wait State VDDCORE set at 1.08V and VDDIO 2.7V to 3.6V @85C
FWS Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 20
1 2 cycles 40
2 3 cycles 60
3 4 cycles 80
4 5 cycles 100
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HIGH
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LOW
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HD;STA
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HD;DAT
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SU;DAT
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SU;STO
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BUF
TWCK
TWD
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