Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
Figure 31-9. Programmable Delays
31.7.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In
this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the
SPI_TDR has no effect.
• Variable Peripheral Select: Data can be exchanged with more than one peripheral without
having to reprogram the NPCS field in the SPI_MR register.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is
used to select the current peripheral. This means that the peripheral selection can be defined for
each new data. The value to write in the SPI_TDR register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)
(1)
+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS
equals to the chip select to assert as defined in Section 31.8.4 (SPI Transmit Data Register) and
LASTXFER bit at 0 or 1 depending on CSAAT bit.
Note: 1. Optional.
CSAAT, LASTXFER and CSNAAT bits are discussed in Section 31.7.3.9 ”Peripheral Deselec-
tion with PDC” .
If LASTXFER is used, the command must be issued before writing the last character. Instead of
LASTXFER, the user can use the SPIDIS command. After the end of the PDC transfer, wait for
the TXEMPTY flag, then write SPIDIS into the SPI_CR register (this will not change the configu-
ration register values); the NPCS will be deactivated after the last character transfer. Then,
another PDC transfer can be started if the SPIEN was previously written in the SPI_CR register.
31.7.3.6 SPI Peripheral DMA Controller (PDC)
In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce
processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is
an optimal means, as the size of the data transfer between the memory and the SPI is either
DLYBCS DLYBS DLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK