Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By
default, DIV parameter is set to 0 which means that the divider is turned off.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0
and 62. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL
input frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before the LOCK bit is set in
PMC_SR, after CKGR_PLLAxR has been written.
Once the CKGR_PLL register has been written, the user must wait for the LOCK bit to be
set in the PMC_SR. This can be done either by polling the status register or by waiting the
interrupt line to be raised if the associated interrupt to LOCK has been enabled in PMC_IER.
All parameters in CKGR_PLLAxR can be programmed in a single write operation. If at some
stage one of the following parameters, MUL or DIV is modified, the LOCK bit will go low to
indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is
constrained to wait for LOCK bit to be set before using the PLL output clock.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the Master Clock Register
(PMC_MCKR).
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is main clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values (1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to main clock.
Once PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in
PMC_SR. This can be done either by polling the status register or by waiting for the interrupt
line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER
register.
The PMC_MCKR must not be programmed in a single write operation. The preferred pro-
gramming sequence for PMC_MCKR is as follows:
• If a new value for CSS field corresponds to PLL Clock,
– Program the PRES field in PMC_MCKR.
– Wait for the MCKRDY bit to be set in PMC_SR.
– Program the CSS field in PMC_MCKR.
– Wait for the MCKRDY bit to be set in PMC_SR.
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
– Program the CSS field in PMC_MCKR.
– Wait for the MCKRDY bit to be set in the PMC_SR.
– Program the PRES field in PMC_MCKR.
– Wait for the MCKRDY bit to be set in PMC_SR.
If at some stage one of the following parameters, CSS or PRES is modified, the MCKRDY
bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet.
The user must wait for MCKRDY bit to be set again before using the Master and Processor
Clocks.