Atmel SAM4S Series, Предварительный информационный лист

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148
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
11.6.6.11 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro-
ducing a 64-bit result.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
Operation
The
UMULL
instruction interprets the values from
Rn
and
Rm
as unsigned integers. It multiplies
these integers and places the least significant 32 bits of the result in
RdLo
, and the most signifi-
cant 32 bits of the result in
RdHi
.
The
UMLAL
instruction interprets the values from
Rn
and
Rm
as unsigned integers. It multiplies
these integers, adds the 64-bit result to the 64-bit unsigned integer contained in
RdHi
and
RdLo
,
and writes the result back to
RdHi
and
RdLo
.
The
SMULL
instruction interprets the values from
Rn
and
Rm
as two’s complement signed integers.
It multiplies these integers and places the least significant 32 bits of the result in
RdLo
, and the
most significant 32 bits of the result in
RdHi
.
The
SMLAL
instruction interprets the values from
Rn
and
Rm
as two’s complement signed integers.
It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in
RdHi
and
RdLo
, and writes the result back to
RdHi
and
RdLo
.
Restrictions
In these instructions:
• do not use SP and do not use PC
•
RdHi
and
RdLo
must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
op is one of:
UMULL
Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL
Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo
are the destination registers. For UMLAL and SMLAL they also hold the accumulating
value.
Rn, Rm are registers holding the operands.