Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
11.11 Memory Protection Unit (MPU)
The MPU divides the memory map into a number of regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
• independent attribute settings for each region
• overlapping regions
• export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4
MPU defines:
• eight separate memory regions, 0-7
• a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with
the highest number. For example, the attributes for region 7 take precedence over the attributes
of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but
is accessible from privileged software only.
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data
accesses have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault. This causes a fault exception, and might cause the termination of
the process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the
process to be executed. Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see
“Memory Regions, Types and
Attributes”
).
Table 11-34
shows the possible MPU region attributes. These include Share ability and cache
behavior attributes that are not relevant to most microcontroller implementations. See
“MPU Con-
figuration for a Microcontroller”
for guidelines for programming such an implementation.
Table 11-34. Memory Attributes Summary
Memory Type Shareability Other Attributes Description
Strongly- ordered - -
All accesses to Strongly-ordered memory occur in program order. All
Strongly-ordered regions are assumed to be shared.
Device
Shared - Memory-mapped peripherals that several processors share.
Non-shared - Memory-mapped peripherals that only a single processor uses.
Normal
Shared Normal memory that is shared between several processors.
Non-shared Normal memory that only a single processor uses.