Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Afterwards, combining the sequential prefetch (described in Section 19.4.2.2 ”Code Read Opti-
mization” ) through the loop body with the fast read access to the loop entry cache, the whole
loop can be iterated with no wait-state.
Figure 19-4. Code Loops Optimization
19.4.2.4 Data Read Optimization
The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit)
prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system
performance. This buffer is added in order to store the requested data plus all the data contained
in the 128-bit (64-bit) aligned data. This speeds up sequential data reads if, for example, FWS is
equal to 1 (see
Figure 19-5 ). The data read optimization is enabled by default. If the bit SCODIS
in Flash Mode Register (EEFC_FMR) is set to 1, this buffer is disabled and the data read is not
optimized anymore.
Note: No consecutive data read accesses are mandatory to benefit from this optimization.
Figure 19-5. Data Read Optimization for FWS = 1
L
n
L
n-1
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n-2
L
n-3
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n-4
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n-5
L
5
L
4
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3
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2
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1
L
0
B
1
B
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7
B
0
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1
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0
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b0
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b0
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b1
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p0
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p1
Backward address jump
2x128-bit loop entry
cache
2x128-bit prefetch
buffer
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0
Loop Entry instruction
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n
Loop End instruction
Flash Memory
128-bit words
M
b0
Branch Cache 0
M
b1
Branch Cache 1
M
p0
Prefetch Buffer 0
M
p1
Prefetch Buffer 1
Flash Access
Buffer (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15 Bytes 16-31
Bytes 0-15
Bytes 0-3
4-7 8-11 12-15 16-19 20-23 XXX
Bytes 16-31
@Byte 0 @ 4 @ 8 @ 12 @ 16 @ 20 @ 24 @ 28 @ 32 @ 36
XXX Bytes 32-47
24-27 28-31 32-35